RE: ideal CPU/Memory relation

The correct answer is “it depends.” Martin gave an example of a particular sweet spot construction for a particular known job mix.  

As general architectures develop, we’re probably (eventually) going to see curved populations of cpus similar to Seymore Cray’s design, but on a tiny scale and with the relationship of cpu and memory inverted so that you can fit as many cpus as needed to drive maximum utilization of memory bandwidth within the distance of speed of light requirements.  

Cray’s computer was the only one that broke the Lupfer & Long Spread Modeling Language regression test. Greg Lupfer told me I had one result wrong in my port of the base code to the Cray and I thought he was right. It took me two days to hand simulate the calculation at Cray’s number length, which showed that it was less round-off error on the Cray that made the answer different (slightly more accurate). I had over twenty hardware/opsys combinations on my resume when I left L&L, which no one believed, so eventually I took all that off. I enjoyed being the porting group of the company, mostly because (except for a couple days in this one case) the regression test proved whether the port was correct. The hardest one was “The machine that had a man for a soul” from Data General, because it was really hard (for me) to get the backwards carriage return line feed to work correctly on DEC printers. A close second was MVS TSO, because I had to hand write assembler interfaces that everyone else but IBM had made callable system libraries from Fortran.  

Clay’s answer of 42 is also a correct way of saying “it depends.”  

I wonder which communications bandwidth between the components of a computer will be the pacing item of performance in ten years! I really doubt it will ever be persistent media again (outside the area of business continuation, but recovery and backup are askew from performance solving problems).  

I wouldn’t be surprised to see additional layers (rings?, oh, let it be rings!) of memory interdigitated with cpus in NUMA groups that have different densities and speeds. We’ll see…  

What a great thread…      

From: oracle-l-bounce_at_freelists.org [mailto:oracle-l-bounce_at_freelists.org] On Behalf Of Tanel Poder Sent: Friday, August 19, 2022 5:17 PM
To: jhg_at_isnordic.dk
Cc: Clay.Jackson_at_quest.com; frits.hoogland_at_gmail.com; Lothar Flatz; Stefan Koehler; oracle-l_at_freelists.org Subject: Re: ideal CPU/Memory relation  

My understanding is that you'd want "balanced configuration" for your DIMMs if you want max memory performance (and not just amount of RAM).  

So, the best is to have an integer multiple of memory channels DIMMs populated. So if you have a single socket Xeon with 6 memory channels, but 8 DIMM slots on the motherboard, for best memory perf you'd put 6 DIMMs there, not 8 (of course, following the vendor guidelines of which slots to populate first). Similarly, if your motherboard has 16 DIMM slots, then you'd populate only 12 slots if your CPU has only 6 memory channels.  

https://www.wwt.com/article/memory-population-guidelines-for-intel-3rd-gen-xeon-scalable-processors  

Tanel  

On Fri, Aug 19, 2022 at 4:40 PM Joe H-Grosse <jhg_at_isnordic.dk> wrote:

Hi,
If you/we are talking NUMA Architecture (vs UMA SMP Systems) and DIMM population into DIMM sockets within the context of a multi-CPU NUMA hardware, then assuming the question asked is "how much RAM is the right amount of RAM for a given number of CPU's for a given specific system (X)", then part of the answer might be as follows:-

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