Senior Layout Designer, San Diego

Senior Layout Designer: San Diego
Looking for a team player capable of working with a highly competent group of engineers. the IC CAE and Layout team is a small group; therefore competency within your field and ability to independently perform a wide array of layout requirements is important. The people, the projects, and the tools will keep your interest, as well as your career on the edge of wireless technology. In this role you will be able to participate in setting state-of-the-art layout environment. Block level layout
Chip floorplanning
Layout verification (DRC, LVS)
Layout project lead
Interface with Place & Route service company Requirements: Seeking highly motivated self-starter with 5 years minimum layout experience. Ability to take a chip from floorplan to tapeout is essential. Knowledge of Cadence Virtuoso/VirtuosoXL layout editor. Also, layout experience with submicron processes (0.35um CMOS, 0.25um CMOS and Cadence Diva DRC/LVS layout verification. The following experience would be a plus: analog layout experience with BiCMOS or Bipolar processes and Unix. tariq_at_nsquare.com
Tel: 909 765 1473 Received on Tue May 01 2001 - 21:58:12 CEST