RE: ideal CPU/Memory relation

No (Oracle Database) on ARM64 yet; but MySQL, Berkeley DB and client - it's coming and I think it's a given that memory utilization and tuning will be "different".

All the theoretical discussions and experimentation are great! A great way to "while away the hours", keep the academics on the "publish and still perish" treadmill and of course keep me and many other folks have responded employed as "experts". But I'm continually amused at the number of folks with "real jobs", like caretakers of data (aka DBAs) for those businesses that are supposed to be producing something besides "more data", who insist on trying to eke out that last 1% of performance from some piece of hardware or another while ignoring mundane things like backup and recovery or keeping their data and systems secure and functioning above 99% or even less availability.

And yes, it ALWAYS "depends" and 42 is ALWAYS the correct ratio.

Clay Jackson

From: oracle-l-bounce_at_freelists.org <oracle-l-bounce_at_freelists.org> On Behalf Of Mladen Gogala Sent: Friday, August 19, 2022 9:37 PM
To: oracle-l_at_freelists.org
Subject: Re: ideal CPU/Memory relation

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On 8/19/22 16:10, Tanel Poder wrote:
Oh, the world is changing, PCIe (especially PCIe 5.0 and future 6.0) latency and throughput are so good, so that it's getting pretty close to the RAM speed as far as the transport goes. So (now that Intel killed Optane<https://nam12.safelinks.protection.outlook.com/?url=https%3A%2F%2Ftanelpoder.com%2Fposts%2Ftesting-oracles-use-of-optane-persistent-memory%2F&data=05%7C01%7Cclay.jackson%40quest.com%7Ceb116e7d64484da2443608da8265a55d%7C91c369b51c9e439c989c1867ec606603%7C0%7C0%7C637965670336362721%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=gon31leIdfTQr%2BV%2BQwcyP7fz0vQ1x%2F0HtDABPeS2L14%3D&reserved=0>) it's worth keeping an eye on the Compute Express Link (CXL) standard. With CPU support, it's basically like cache coherent system memory, but accessed over PCIe5.0+ links. It's even possible to connect large boards full of DRAM to multiple separate compute nodes, so in theory someone could build a CXL-based shared global buffer cache used by the entire rack of servers concurrently, without needing RAC GC/LMS processes to ship blocks around.

And also DDR5 DRAM is emerging fast. You will also need larger L3 and L2 caches, as well as larger TLB. I am waiting for Oracle to make RDBMS available on arm64 Linux architecture. Unfortunately, I haven't found the description of memory channel architecture on multi-core ARM chips. This is the best I've found:

https://en.wikipedia.org/wiki/Comparison_of_ARM_cores<https://nam12.safelinks.protection.outlook.com/?url=https%3A%2F%2Fen.wikipedia.org%2Fwiki%2FComparison_of_ARM_cores&data=05%7C01%7Cclay.jackson%40quest.com%7Ceb116e7d64484da2443608da8265a55d%7C91c369b51c9e439c989c1867ec606603%7C0%7C0%7C637965670336362721%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=lPdkAL4r4lBqB7sbY1LraO%2FFieyDBaCrCQ4tHaX%2FooQ%3D&reserved=0>

Of course, RISC chips use more RAM than CISC chips, so whatever is found to work well for x86_64 processors is unlikely to be adequate for ARM chips. Does anyone have the information of Oracle RDBMS on Linux/arm64 architecture?

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Mladen Gogala

Database Consultant

Tel: (347) 321-1217

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http://www.freelists.org/webpage/oracle-l Received on Sun Aug 21 2022 - 01:26:13 CEST