(no subject)

Silicon Graphics has a new open position in its Mountain View headqarters for a standard cell ASIC layout design engineer. This engineer will be responsible for floorplanning for area, timing, and routability. Responsibilities include place and route of cells from netlists, extraction for LUS, DRC, and tapeout to GDSZ. This engineer will evaluate layouts for timing, signal integrity, and power and clock distribution, making corrections or modifications to vendor cells as needed.

This position requires a BSEE or equivalent, plus four or more years applicable experience in floorplanning, place and route, C programming, and layout of ASIC standard cell design.

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Robert Dexter			rdexter_at_esd.sgi.com
Digital Media Staffing		http://www.sgi.com
Silicon Graphics		phone: 415-933-4036
2011 North Shoreline Blvd.	fax: 415-933-0122
MS 14L-921
Mountain View, CA 94039