From oracle-l-bounce@freelists.org Wed Jul 14 15:12:08 2004 Return-Path: Received: from air189.startdedicated.com (root@localhost) by orafaq.com (8.11.6/8.11.6) with ESMTP id i6EKBhf20733 for ; Wed, 14 Jul 2004 15:11:53 -0500 X-ClientAddr: 206.53.239.180 Received: from turing.freelists.org (freelists-180.iquest.net [206.53.239.180]) by air189.startdedicated.com (8.11.6/8.11.6) with ESMTP id i6EKBV620683 for ; Wed, 14 Jul 2004 15:11:41 -0500 Received: from localhost (localhost [127.0.0.1]) by turing.freelists.org (Avenir Technologies Mail Multiplex) with ESMTP id 7329D72DFDE; Wed, 14 Jul 2004 14:50:04 -0500 (EST) Received: from turing.freelists.org ([127.0.0.1]) by localhost (turing [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 25384-22; Wed, 14 Jul 2004 14:50:04 -0500 (EST) Received: from turing (localhost [127.0.0.1]) by turing.freelists.org (Avenir Technologies Mail Multiplex) with ESMTP id AE16272CCF8; Wed, 14 Jul 2004 14:50:03 -0500 (EST) Received: with ECARTIS (v1.0.0; list oracle-l); Wed, 14 Jul 2004 14:48:32 -0500 (EST) X-Original-To: oracle-l@freelists.org Delivered-To: oracle-l@freelists.org Received: from localhost (localhost [127.0.0.1]) by turing.freelists.org (Avenir Technologies Mail Multiplex) with ESMTP id D993F72DF12 for ; Wed, 14 Jul 2004 14:48:31 -0500 (EST) Received: from turing.freelists.org ([127.0.0.1]) by localhost (turing [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 24717-78 for ; Wed, 14 Jul 2004 14:48:31 -0500 (EST) Received: from smtp.wangtrading.com (smtp.wangtrading.com [167.206.68.5]) by turing.freelists.org (Avenir Technologies Mail Multiplex) with ESMTP id 455B672DF66 for ; Wed, 14 Jul 2004 14:48:31 -0500 (EST) Received: from imap (Not Verified[192.168.9.50]) by smtp.wangtrading.com with NetIQ MailMarshal (v5.5.5.8) id ; Wed, 14 Jul 2004 16:11:27 -0400 Received: from mladen.wangtrading.com (mladen.wangtrading.com [::ffff:192.168.3.47]) (TLS: TLSv1/SSLv3,256bits,AES256-SHA) by imap with esmtp; Wed, 14 Jul 2004 16:13:25 -0400 Received: from mladen (localhost.localdomain [127.0.0.1]) by mladen.wangtrading.com (8.12.8/8.12.8) with ESMTP id i6EKDPAk021639 for ; Wed, 14 Jul 2004 16:13:25 -0400 Date: Wed, 14 Jul 2004 16:13:25 -0400 From: Mladen Gogala To: oracle-l@freelists.org Subject: Re: L2 cache vs. faster processor Message-ID: <20040714201325.GC21482@mladen.wangtrading.com> References: <018e01c469d8$60efb0b0$6601a8c0@TerrySutton> Mime-Version: 1.0 Content-type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Content-Disposition: inline In-Reply-To: <018e01c469d8$60efb0b0$6601a8c0@TerrySutton> (from terrysutton@usa.net on Wed, Jul 14, 2004 at 15:23:16 -0400) X-Mailer: Balsa 2.0.17 Lines: 42 X-Mime-Autoconverted: from 8bit to 7bit by courier 0.42 X-Virus-Scanned: by amavisd-new at freelists.org X-archive-position: 5123 X-ecartis-version: Ecartis v1.0.0 Sender: oracle-l-bounce@freelists.org Errors-To: oracle-l-bounce@freelists.org X-original-sender: mladen@wangtrading.com Precedence: normal Reply-To: oracle-l@freelists.org X-list: oracle-l X-Virus-Scanned: by amavisd-new at freelists.org Definitely L2 cache. My numbers may be a little bit out of date, but the story remains the same. L2 cache is a sequential 15ns portion of memory which caches your RAM. L1 cache is very small, typically 64k or 128k set associative RAM. There is also something called TLB which is a fully associative buffer with 64 locations. The rest of your RAM is 50ns SDRAM, with "burst mode". So, what happens in a VM system when program requires the value of the variable in the address X? CPU has to resolve the location X. In order to resolve the location X, it will have to go to memory and fetch the page table first. Then it will look through the page table, find the address and again go to memory and get the page itself. That means that resolution of each address needs 2 accesses to the main memory, which is equally fast, regardless of the CPU. If no L2 cache is present, efficiency of L1 cache is approximately 25%. L1 cache is invalidated as soon as someone issues a jump, like, let's say. a call to a subroutine (fashionable expression is "method"). L2 cache only cache physical pages, in order to help the execution. Together with L1, the typical efficiency is around 70%-90%, depending on the size of L2 cache. One other thing to know is that the speed of waiting is equal on both 3GHZ chip and 2GHZ chip. 3GHZ chip waiting 3 times for 100 nsec access to RAM will spend 300nsec of its time waiting, while 2GHZ chip with L2 cache will be working.... The only programs that will be faster on 3GHZ chip without L2 cache are the ones that are written with locality of reference in mind, and which don't do nasty things like context switches (every system call, like I/O) of call subroutines. Ultimately, the answer depends on what you want to do. If you are a rocket scientist designing ship for the mission to Mars with Carrie Ann Moss, you'll probably want 3GHZ without L2 cache. For oracle, on the other hand, you do want L2 cache. On 07/14/2004 03:23:16 PM, Terry Sutton wrote: > A client is ordering hardware for an Oracle on Linux system, and has to choose between 2.8 GHz Xeon processors with 1MB L2 cache and 3.06 GHz Xeon processors (no L2 cache). Does anyone have any recommendations on the value of L2 cache vs. a faster processor? > --Terry > > ---------------------------------------------------------------- > Please see the official ORACLE-L FAQ: http://www.orafaq.com > ---------------------------------------------------------------- > To unsubscribe send email to: oracle-l-request@freelists.org > put 'unsubscribe' in the subject line. > -- > Archives are at http://www.freelists.org/archives/oracle-l/ > FAQ is at http://www.freelists.org/help/fom-serve/cache/1.html > ----------------------------------------------------------------- > -- Mladen Gogala Oracle DBA Wang Trading LLC Tel: (203) 956-6826 Note: This message is for the named person's use only. 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