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From: Matthew Zito <>
Date: Mon, 7 Jun 2004 12:06:00 -0400
Message-Id: <>

See inline, please.

On Jun 7, 2004, at 10:45 AM, Tim Johnston wrote:

> Excellent... Thanks Matt... I have a couple more questions below if
> you have the chance... Thanks...
> I read some of the stuff about the common memory bus and figured that
> would be an impact... As far as cache, it appears that each core has
> it's own L2 cache... Kind of... They appear to share the bus to the
> L2 but the L2 is doubled from 8 to 16 MB and each core has a dedicated
> 8 MB... They perform some magic to split the address ranges on the L2
> bus and it makes sure that each core can only access the appropriate
> section of the L2... Any thoughts on that?

I'm sorry, I should have been more clear. You're right, its two logically separated cache subsystems, so there's no actual arbitration for memory ranges. But, with a common entry point to the cache, there is a possible choke point. The side effect of logical separation, though, is that (theoretically) context switching from one core to the other continues to involve cache invalidation - not sure whether this is actually the case, but seems logical that it would work this way. I haven't had a chance to dig into the deep processor architecture stuff for the USIV, as we haven't really bumped into it yet.

> Ok... To give this a real world example, if you have a 12 CPU box
> that has an average of 12 processes running CPU bound then moving from
> III to IV doesn't buy you much... But, if you have a 12 CPU machine
> with an average of 24 CPU bound processes then it should help...

That's exactly right - another situation is that if you have 100 running processes with 5 of them being very CPU-heavy, its not going to help that much.

>> The REALLY important thing, though - Oracle counts every core of a
>> multi-core processor <snip>
>> are the way of the future, Oracle has taken a stand early on that
>> every core counts as a processor and must be licensed as such.
> Ah... I hadn't heard this one yet... That could be a big one...
> Thanks!

Yeah, it pretty much removes any argument for the US IV, in my mind. I'm a little peeved that Sun is muddying the waters by claiming that each UltraSparc IV is a "processor" - the amusing side effect is their marketing capital does linguistic backflips with terms like "Chip MultiThreading - CMT". The goal is to encourage people to see the chips as a single processor, and not see the need to doubly license per-cpu software, which I find disingenuous.

I'm curious as to whether tiered software such as veritas will consider USIV-equipped servers as a higher tier than their USIII brethren. The tiers have always been fairly arbitrary, so I wouldn't be surprise if there was a big jump there from the III to the IV.


Matthew Zito
GridApp Systems
Cell: 646-220-3551
Phone: 212-358-8211 x 359

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Received on Mon Jun 07 2004 - 11:02:07 CDT

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